
`define USE_YOSYS
`ifdef USE_YOSYS
(* blackbox *)
module cycloneive_clkctrl(
    ena,
	inclk,
	clkselect,
	devclrn,
	devpor,
	outclk
    );
	input wire ena;
	input wire[3:0] inclk;
	input wire[1:0] clkselect;
	input tri devclrn;
	input tri devpor;
	output wire outclk;
endmodule

module def_clk (
    clk_in,
    clk_out
);
    input wire clk_in;
    output wire clk_out;



    tri devclrn;
    tri devpor;
    tri devoe;
    wire outclk;
    // Location: CLKCTRL_G2
cycloneive_clkctrl inputclkctrl (
	.ena(1'b1),
	.inclk({1'b1,1'b1,1'b1,clk_in }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(outclk ));
// synopsys translate_off
defparam inputclkctrl .clock_type = "global clock";
defparam inputclkctrl .ena_register_mode = "none";
// synopsys translate_on


    assign clk_out = outclk;
endmodule

`else
module def_clk (
    clk_in,
    clk_out
);
    input wire clk_in;
    output wire clk_out;
    assign clk_out = clk_in;
endmodule
`endif

module io_def (
    clk,
    ledout,
    gpio_pin
);
    input wire          clk;
    output wire[3:0]     ledout;
    input wire[3:0]     gpio_pin;
    reg [3:0] ledoutr = 'd0;
    assign ledout[3:1] = ledoutr[3:1];
    assign ledout[0] = clk;

    def_clk clkctrl(clk,outclk);
    def_clk clkctrl2(gpio_pin[2]&clk,outclk2);

    wire d =   outclk & gpio_pin[1];
    wire d2 =  outclk & gpio_pin[2];
    reg value = 0;
    always @(posedge outclk) begin
        ledoutr[3:2] <= ledoutr[3:2] + 2'd1;
    end

    always @(posedge outclk2) begin
        ledoutr[1:0] <= ledoutr[1:0] + 2'd1;
    end

endmodule


